In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures that include active or operable portions of semiconductor devices. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material including, but not limited to, bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including, but not limited to, the semiconductive substrates described above.
Modern integrated circuits are manufactured by an elaborate process in which a large number of electronic semiconductor devices are integrally formed on a small semiconductor substrate. The conventional semiconductor devices that are formed on the semiconductor substrate include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate.
In order to compactly form the semiconductor devices, the semiconductor devices are formed on varying levels of the semiconductor substrate. Consequently, one step in the process of manufacturing an integrated circuit is to electrically connect the discrete semiconductor devices that are located on nonadjacent structural levels of the integrated circuit. One manner of electrically connecting these semiconductor devices is with an interconnect structure. The interconnect structure generally comprises a region of conducting material that is formed between the semiconductor devices or portions of the semiconductor devices that are being placed in electrical communication. The interconnect structure serves as a conduit for delivering electrical current between the semiconductor devices. Specific types of interconnect structures include local interconnects, contacts, buried contacts, vias, plugs, and filled trenches. Resistors and diodes also function as interconnect structures when making electrical contact between separate semiconductor devices.
The semiconductor industry is constantly under market demand to increase the speed at which integrated circuits operate, to increase the density of devices on the integrated circuits, and to reduce the price of the integrated circuits. To accomplish this task, the semiconductor devices used to form the integrated circuits are continually being increased in number and decreased in dimension in a process known as miniaturization. Interconnect structures and existing processes of forming interconnect structures must in turn be adapted to facilitate the constant miniaturization of the semiconductor devices for which the interconnect structures are used to connect.
One component of the integrated circuit that is becoming highly miniaturized is the active region. The active region is a doped area on a silicon substrate of the semiconductor substrate that is used together with other active regions to form a diode or transistor. The miniaturization of the active region complicates the formation of the interconnect structure in that, in order to maintain sufficient conductivity, the interconnect structure must be formed in exact alignment with the active region. Also, the area of the interconnect structure interfacing with the active region must be maximized. Thus, less area exists as tolerance for misalignment of the interconnect structure.
The active region is also becoming increasingly shallow. Consequently, measures must be taken in forming the interconnect structure and overlying semiconductor device to prevent silicon from the active region from being consumed. This shallowness of the active region often necessitates a planar interconnect structure interface that minimizes penetration of the original active region surface. The shallowness of the active region also often necessitates the use of a material other than the traditionally used aluminum in the interconnect structure for interfacing with the active region. Direct contact with aluminum causes the aluminum to diffuse into the silicon of the active region and to form spikes that can penetrate entirely through the active region, causing adverse electrical consequences.
These demands on the interconnect structure have not been adequately met by the existing conventional technology for forming the interconnect structure. As a result, formation of the interconnect structure is currently a limiting factor in the miniaturization of integrated circuits.
One type of interconnect structure frequently used in the conventional technology is the buried contact. The buried contact is a region of polysilicon that makes direct contact between the interconnect structure and the active region, eliminating the need for a metal link. In forming the buried contact, a window is opened in a thin gate oxide over the active region that the interconnect structure is to electrically connect. Thereafter, polysilicon is deposited in direct contact with the active region in the opening but is isolated from the underlying silicon substrate of the semiconductor substrate by gate oxide and by field oxides everywhere else. An ohmic contact is formed at the polysilicon and active region interface by diffusion into the active region of a dopant present in the polysilicon. This dopant diffusion into the active region in effect merges the polysilicon with the active region. A layer of insulating film is then deposited to cover the buried contact.
The buried contact is so termed because a metal layer can cross over the active region forming the buried contact without making an electrical connection to the buried contact. The use of a buried contact eliminates spiking and provides an additional benefit in that it makes available an additional level for forming interconnect structures on the integrated circuit. This additional level allows circuit connections to be formed in one step and then in a later step to be connected with surface level metal interconnect lines. The additional level also adds significant interconnect structure routing flexibility to the integrated circuit design.
The buried contact also exhibits certain shortcomings. For instance, it is difficult at greater miniaturization levels to exactly align the contact hole with the active region when patterning and etching the contact hole. As a result, topographies near the active region can be penetrated and damaged during etching of the contact hole. For example, a misaligned buried contact hole etch can notch and, therefore, damage a gate stack. The damage reduces the performance of the active region and neighboring structures, which causes a loss of function of the semiconductor device being formed and possibly a defect condition in the entire integrated circuit. To remedy the problems associated with the buried contact, the prior art uses compensation techniques such as an etch stop barrier. These compensation techniques are time consuming and thus reduce throughput.
The active region is also, in order to compensate for the aforementioned complications, typically constructed with larger dimensions. As a result, the degree to which the active region can be miniaturized under the conventional technology is limited.
One improvement in conventional interconnect structures is the silicided contact. Formation of the silicided contact involves a metal such as titanium that, when deposited over the active region, combines with the silicon of the active region to form a low resistivity silicide. In forming the conventional silicided contact, the active region is formed and a layer of titanium is then deposited over the exposed active region. The semiconductor substrate is then heated with an annealing process. The annealing process causes a silicidation reaction to occur, creating titanium silicide everywhere that titanium is in contact with the silicon. Where the titanium is not in contact with silicon, the titanium remains unreacted. The unreacted titanium can then be selectively removed through the use of an etchant that does not attack the silicide. As a result, each exposed active region is substantially covered by a silicide film that is self-aligned to the top surface of the active region. The silicide film forms a conductive interface with the active region. A dielectric layer is then deposited over the active region and a contact hole is opened in the dielectric layer down to the silicide film. Thereafter, aluminum is deposited into the contact hole to make contact with the silicide film. The silicide film intervening between the aluminum and the active region allows the use of aluminum for filling the contact holes without the occurrence of spiking.
Further advantages of this method include a low contact resistance and a large area of contact between the active region and the silicide. Nevertheless, the self-aligned silicide contact also has drawbacks in that it requires numerous steps to form, reducing integrated circuit fabrication throughput. It also consumes a significant portion of the active region in being formed and cannot be sacrificially etched without harming the active region.
Another need in the art involves the fabrication of a memory circuit such as the DRAM, where capacitors must be placed in electrical contact with the active region. The formation of a DRAM capacitor typically requires a sacrificial region of polysilicon known as a landing pad above the active region to protect the active region against damage. The landing pad protects the underlying active region by acting as a buffer over the active region that can be sacrificially etched.
The conventional self-aligned silicide contact cannot be used as a landing pad. A further shortcoming of using the landing pad is that it is not always possible to conduct the sacrificial etching evenly across the whole semiconductor substrate. The center of the semiconductor substrate, in many instances, is etched at a faster rate than the edges. Thus, landing pads located at the center of the semiconductor substrate may be etched through, allowing the etching process to come in contact with the active region before landing pads at the edges of the semiconductor substrate are sufficiently etched. As a consequence, damage to active regions at the center of the semiconductor substrate can occur. Accordingly, an interconnect structure that can function as a sacrificial landing pad, that can be self aligned, and that effectively protects the active region against over-etching is also needed in the art.
In a further problem in the art, conventional capacitors exhibit the problem of leakage paths from the base of the capacitor where the landing pad is formed into the underlying silicon substrate. The leakage reduces the amount of time the capacitor is able to hold a charge. Accordingly, a method for overcoming leakage through the base of the capacitor is also needed.
A further structure that is formed on the semiconductor substrate during the integrated circuit fabrication process is a region of insulating material known as the isolation region. The isolation region is used to electrically isolate P-channel regions from N-channel regions on CMOS integrated circuits, to prevent a destructive interaction between N-doped and P-doped regions of CMOS devices known as latch-up, and to separate closely spaced electrical devices such as capacitors. A need also exists in the art for a method for fabricating isolation regions with fewer steps in order to increase integrated circuit fabrication throughput and lower integrated circuit fabrication costs.
Accordingly, from the above discussion, it is apparent that what is needed in the art is a method whereby interconnect structures can be formed in a manner that maintains better control over device geometries in order to allow greater integrated circuit miniaturization. The formation of an interconnect structure that can be sacrificially etched without damaging an adjacent active region is also desirable. An interconnect structure is also needed that is self-aligned, that can serve as a sacrificial landing pad, that can prevent over-etch, and that can reduce capacitor leakage paths. It would be further desirable to be able to combine interconnect structure fabrication and isolation region fabrication to save process steps.